MICROPROCESSOR TECHNIQUES LAB ASSIGNMENT 1 8086 ARCHITECTURE The 8086 microprocessor is a 16 bit processor The term 16 bit means that it s ALU registers and most instructions are designed to work on 16 bits 8086 has 16 bit data lines and 20 bit address lines Hence it can access up to 1 GB of memory 8086 microprocessor does 2 stage pipelining i e it overlaps fetching of an instruction and execution Hence the internal structure or architecture of 8086 is divided into two units Bus Interface Unit BIU Execution Unit EU Bus Interface Unit It provides interface of the 8086 processor to the I O devices and external memory Functions Generates 20 bit physical address for memory access Fetches instruction from memory Transfers data between I O devices and external memory Supports pipelining using 6 byte instruction queue Reads and writes data from and to ports and memory The components of BIU are Instruction Queue Size 6 byte FIFO First In First Out RAM Supports pipelining by fetching next instruction while the present instruction is being executed Fetches next 6 instruction bytes from Code Segment and stores it in the queue Execution Unit EU takes instructions from the queue and executes it The queue is refilled when at least 2 bytes are empty Segment Registers There are 4 16 bit segment registers 

These registers hold the starting addresses for each respective segment Code Segment CS Data Segment DS Stack Segment SS Extra Segment ES 3 Instruction Pointer 16 bit register Holds offset of the instruction in CS It is incremented after every instruction fetch Physical Address Generation circuit It generates 20 bit physical address using the offset address and the segment address Formula Physical address Segment address x 10H Offset Execution Unit EU Fetches instructions from Queue in BIU and then decodes and executes them Contains ALU hence performs arithmetic and logic operations Performs internal data transfer operations within the microprocessor No direct connection with system buses Performs operations on data through BIU Functional Units are General Purpose Registers There are 4 16 bit general purpose registers AX BX CX AND DX These are available to programmers for storing values during programs Each of these registers can be divided into two 8 bit registers AL AH BL BH CL CH etc 2 Special Purpose Registers Stack Pointer SP 16 bits Holds offset address of the top of the Stack Base Pointer BP 16 bits Holds offset address of any location in the stack segment Used to access random locations of the stack Source Index SI 16 bits Used to hold offset address for Data Segment Can be used for other segments using Segment Overriding Holds offset address of source data in Data Segment during string operations Destination Index DI 16 bits Used to hold the offset address for Extra Segment Can also be used for other segments using Segment Overriding Holds offset address of destination in Extra Segment during string operations 3 ALU Arithmetic Logic Unit 16 bit ALU Performs 8 bit and 16 bit arithmetic and logical operations 4 Operand register 16 bit register Used by control register to hold the operands temporarily Not available to the programmer 5 Instruction Register and Instruction Decoder The EU fetched opcode from the queue is stored into the instruction register

The instruction decoder decodes it and sends the information to the control circuit for execution 6 Flag registers 16 bit register but uses only 9 bits i e has 9 flags These flags are of two types 6 Status flags Affected by ALU after every arithmetic or logic operation Gives status of current result 3 Control flags Used to control certain operations Changed by the programmer THE PROGRAMMER S MODEL The 8086 microprocessor has a visible programmer s model because programmers can use registers during operations i e registers are visible to the programmers Data registers Also called general purpose registers Store operands and results 16 bit registers AX Also known as accumulator Stores operands for arithmetic operations BX Used as a base register Holds the starting base location of a memory region within a data segment CX Defined as a counter Used in loop instruction to store loop counter DX Used to contain I O port address for I O instruction Pointer and index registers Stack Pointer SP Base Pointer BP Instruction Pointer IP Stack Index SI Data Index DI Segment Registers Code Segment CS Data Segment DS Stack Segment SS Extra Segment ES Flags Status Registers C carry Holds the carry after addition or the borrow after subtraction

Also indicates error conditions as dictated by some programs and procedures P parity Logic 0 for odd parity and a logic 1 for even parity A auxiliary carry Holds the half carry after addition or the borrow after subtraction between bits positions 3 and 4 of the result Z zero Shows that the result of an arithmetic or logic operation is zero Z 1 means result is zero Z 0 means result is not zero S sign Holds the arithmetic sign of the result after an arithmetic or logic instruction executes If S 1 the sign bit negative if S 0 the sign bit is positive T trap If the T 1 the microprocessor interrupts the flow of the program on conditions as indicated by the debug registers and control registers lf T 0 the trapping feature is disabled I interrupt Controls the operation of INTR interrupt request If I 1 INTR pin is enabled if I 0 INTR pin is disabled D direction Selects either the increment or decrement mode for the Dl and or SI registers during string instructions If D 1 the registers are decremented if D 0 the registers are incremented O overflow Indicates that the result has exceeded the capacity of the machine

Write and Proofread Your Essay
With Noplag Writing Assistance App

Plagiarism Checker

Spell Checker

Virtual Writing Assistant

Grammar Checker

Citation Assistance

Smart Online Editor

Start Writing Now

Start Writing like a PRO