Essay Example on MICROPROCESSOR TECHNIQUES LAB ASSIGNMENT

MICROPROCESSOR TECHNIQUES LAB ASSIGNMENT 1 8086 ARCHITECTURE The 8086 microprocessor is a 16 bit processor The term 16 bit means that it s ALU registers and most instructions are designed to work on 16 bits 8086 has 16 bit data lines and 20 bit address lines Hence it can access up to 1 GB of memory 8086 microprocessor does 2 stage pipelining i e it overlaps fetching of an instruction and execution Hence the internal structure or architecture of 8086 is divided into two units Bus Interface Unit BIU Execution Unit EU Bus Interface Unit It provides interface of the 8086 processor to the I O devices and external memory Functions Generates 20 bit physical address for memory access Fetches instruction from memory Transfers data between I O devices and external memory Supports pipelining using 6 byte instruction queue Reads and writes data from and to ports and memory The components of BIU are Instruction Queue Size 6 byte FIFO First In First Out RAM Supports pipelining by fetching next instruction while the present instruction is being executed Fetches next 6 instruction bytes from Code Segment and stores it in the queue Execution Unit EU takes instructions from the queue and executes it The queue is refilled when at least 2 bytes are empty Segment Registers There are 4 16 bit segment registers 

Also indicates error conditions as dictated by some programs and procedures P parity Logic 0 for odd parity and a logic 1 for even parity A auxiliary carry Holds the half carry after addition or the borrow after subtraction between bits positions 3 and 4 of the result Z zero Shows that the result of an arithmetic or logic operation is zero Z 1 means result is zero Z 0 means result is not zero S sign Holds the arithmetic sign of the result after an arithmetic or logic instruction executes If S 1 the sign bit negative if S 0 the sign bit is positive T trap If the T 1 the microprocessor interrupts the flow of the program on conditions as indicated by the debug registers and control registers lf T 0 the trapping feature is disabled I interrupt Controls the operation of INTR interrupt request If I 1 INTR pin is enabled if I 0 INTR pin is disabled D direction Selects either the increment or decrement mode for the Dl and or SI registers during string instructions If D 1 the registers are decremented if D 0 the registers are incremented O overflow Indicates that the result has exceeded the capacity of the machine