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MICROPROCESSOR TECHNIQUES LAB ASSIGNMENT 1 8086 ARCHITECTURE The 8086 microprocessor is a 16 bit processor The term 16 bit means that it s ALU registers and most instructions are designed to work on 16 bits 8086 has 16 bit data lines and 20 bit address lines Hence it can access up to 1 GB of memory 8086 microprocessor does 2 stage pipelining i e it overlaps fetching of an instruction and execution Hence the internal structure or architecture of 8086 is divided into two units Bus Interface Unit BIU Execution Unit EU Bus Interface Unit It provides interface of the 8086 processor to the I O devices and external memory Functions Generates 20 bit physical address for memory access Fetches instruction from memory Transfers data between I O devices and external memory Supports pipelining using 6 byte instruction queue Reads and writes data from and to ports and memory The components of BIU are Instruction Queue Size 6 byte FIFO First In First Out RAM Supports pipelining by fetching next instruction while the present instruction is being executed Fetches next 6 instruction bytes from Code Segment and stores it in the queue Execution Unit EU takes instructions from the queue and executes it The queue is refilled when at least 2 bytes are empty Segment Registers There are 4 16 bit segment registers
