Multipliers play a vital role in today's Digital Signal Processing DSP Microprocessors and in various other applications Modified Radix 4 Booth Multipliers are often preferred due to their high performance obtained by encoding the multiplier bit which reduces the number of partial product generation to half Instead of performing addition using standard parallel adders Wallace tree uses modified Carry Save Adder CSA and Carry Select Adder CSLA By using these high speed adders product is obtained in less time The no of partial product stages can be further reduced by using modified CSA and propagation delay is reduced by CSLA Finally the functionality of Modified Radix 4 Booth Multiplier is verified by implementing it in the design of low pass FIR Filter The Verilog code is simulated using INCISIV and synthesized using Cadence Encounter RTL compiler Simulation results at 180nm and 45nm technology is provided The result shows that the proposed Modified Radix 4 Booth Multiplier is more efficient in terms of power and delay when compared with conventional booth encoder and Wallace Tree Multiplier Index Terms Modified Radix 4 Booth Multiplier Booth encoder Wallace tree CSA CSLA signed unsigned bits 1
