Essay Example on The Study Of Architecture And Programming Model Of 8086

The Study Of Architecture And Programming Model Of 8086 Architecture of 8086 Fig 1 Architecture or functional block of 8086 microprocessor As shown in the above Fig 1 the CPU of 8086 is divided into two parts 1 BIU Bus Interface Unit 2 EU Execution Unit 1 BIU Bus Interface Unit The function Of BIU is to send address to a Fetch the instruction or data from memory b Write the data to memory c Write the data to the port d Read data from the port Various Section of the BIU are given below Segment Registers BIU has 4 segment registers of 16 bit each i e CS DS SS and ES Code Segment CS Is used to address a memory location in the code segment of the memory where the op code of program is stored Data Segment DS Is the register which points to segment of memory where the data is stored Stack Segment SS Is the register used to point out the stack location in stack segment of the memory and used to store data temporarily on the stack Extra Segment ES Is to address the segment which is additional data segment used to store data 

The memory pointers are used to point or address the particular memory location in memory Instruction queue IQ Queue To increase the execution speed BIU fetches as many as six instruction bytes ahead to time from memory All the six bytes are then held in first in first out 6 byte register called instruction queue IQ Then all bytes have to be given to EU one by one This pre fetching operation of BIU may be in parallel with the execution operation of EU which improves the speed of execution of instruction 2 Execution Unit EU The functions of execution unit are a To tell BIU where to fetch the instruction or data from b To decode the instructions c To execute the instruction The EU contains the control circuitry to perform various internal operations a decoder in EU decodes the instruction fetched from memory to generate different internal or external control signal required to perform the operations EU has 16 bit ALU which can perform arithmetic and logical operations on 8 bit as well as 16 bit data Flag register in EU is of 16 bit is given below Fig 2 Flag Register Format of 8086 These register contain nine active flags Five flags in the lower byte of the register are similar to 8085 flag register 8086 flags are divided in two parts Status flags and Control flags Status Flags Carry Flag CF It is set to 1 if there is carry out of the MSB position i e resulting from an addition or if a borrow is needed at MSB during substraction Auxillary Carry AF If an operation performed in ALU generates a carry borrow from lower nibble i e D0 D3 to upper nibble i e D4 D7 the AF flag is set i e carry given by D3bit to D4 is AF flag Parity Flag PF This flag is used to indicate the parity of result If lower order 8 bits of result of an operations contains even number if 1 the parity flag is set and for odd number of 1 the parity flag is reset Zero Flag ZF It is set if the result of arithmetic or logical operation is zero else it will be reset Sign Flag SF In sign magnitude format the sign of number is indicated by MSB bit If the result of operation is negative sign flag is set The sign flag is replica of MSB bit of result Overflow Flag OF 

In case of the signed arithmetic operation the overflow flag is set if the result is too large to fit in the numbers bits available to accommodate it The overflow flag has no significance in unsigned arithmetic operation Control Flags Trap Flag TF It is used for single step control It allows user to execute one instruction of a program at a time for debugging When trap flag is set the program can be run in single step mode Interrupt Flag IF It is an interrupt enable disable flag If it is set the maskable interrupts INTR of 8086 is enabled and if it is reset the interrupts is disable Direction Flag DF The direction flag is used in string operation If DF is set string bytes are read or write from higher memory address to lower memory address If DF is reset the string bytes are read or write from lower memory address to higher memory address Programming Model Of 8086 The programming model of the 8086 through the Pentium II s considered to be program visible because its registers are used during application programming and are specified by the instructions Other registers detailed later in this chapter are considered to be program invisible because they are not addressable directly during applications programming but may be used indirectly during system programming Only the 80286 and above contain the program invisible registers used to control and operate the protected memory system Given below figure 2 1 Illustrates the programming model of the 8086 through the Pentium II microprocessor The programming model contains 8 16 and 32 bit registers The 8 bit registers are AH AL BH BL CH CL DH and DL and are referred to when an instruction is formed using these two letter designations The 16 bit registers are AX BX CX DX SP BP DI SI IP FLAGS CS DS ES SS FS and GS The extended 32 bit registers are EAX EBX ECX EDX ESP EBP EDI ESI EIP and EFLAGS