Essay Example on Multipliers play a vital role in today's Digital Signal Processing

INTRODUCTION In digital computing multiplication operation is basically considered as an arithmetic operation as it uses adders and logic gates to generate the output Shift Add algorithm is the basic process used by the multipliers When compared with adders and subtractors multipliers are more complex Hence while designing a multiplier using VLSI design are power and speed are the three major factors which are to be considered Multiplication operation consists of partial product generation and adding these partial product stages to obtain the final product Mainly the speed of operation depends on the adders and number of partial product stages Thus the performance of the entire system depends on the speed of the multiplication process used High speed Booth Multipliers are used to reduce the power consumption of multiplication operation which in turn increases the speed of the entire system Irregular partial product array is produced due to the use of extra partial product bits in the LSB of partial product stages which increases the number of partial product stages A simple advancement for generating regular partial product array with reduced number of partial product stages is used which lowers the complexity and design constraint of booth multipliers Modified Booth Sum S MB form is used in multipliers recoding technique 

This uses only one adder and parallel multiplier and due to the use of redundant signed digit accuracy is lost In Wallace tree formation optimized Carry Select Adder is used in the final addition process to eliminate the redundant logic operation which is data dependent Implementation of signed and unsigned multiplier uses hybrid adders along with conditional carry adder and conditional sum adder to reduce delay with increased power consumption By using non redundant radix 4 signed digit encoding multiplier bits are pre encoded and stored in ROM which is area and power efficient Approximate computing is useful when accuracy is not considered as a major parameter Approximate Wallace tree formation is used to generate the regular partial product array Error may appear due to the use of approximation technique which produces only the approximate product and not the actual product Instead of using fast adders in the final addition stage redundant binary adders are used which reduces delay Approximate Wallace tree multipliers are used for error tolerant applications due to the power and area efficiency To reduce critical path carry in prediction is used which increases the power consumption In Wallace tree formation stages compressors or counters are mainly used to add the partial products Approximate compressors are proposed in and used in Dadda Multiplier Approximate adders are designed in which does not take into account of the carry propagation between partial products 

By applying hybrid approximation technique power savings for similar error values is obtained Approximate adders are used in the design of radix 8 booth multiplier which uses two bit adder for generating the odd multiples of the multiplicand In Wallace tree formation stage Carry Save Adder plays a vital role in reducing the partial product generation stages Using multiplexer based full adders in CSA structure power and delay is reduced Most conventional multiplier design considers the partial product accumulation stage and mostly they operate on unsigned numbers In this paper two radix 4 modified booth encoding technique is designed and synthesized In this regular partial product array is obtained by using Wallace tree structure Finally the functionality of the proposed booth multiplier is verified by implementing in FIR filter Simulation area and power are also obtained for both multiplier and filter This paper is organized as follows Section 2 presents the design of Modified Radix 4 Booth Multiplier based on two approximate encoders Section 3 presents the Wallace tree structure in Wallace tree multiplier Section 4 presents the implementation of the proposed multiplier in FIR filter operation to verify the functionality of the proposed multiplier Simulation results on area power delay for different technology is provided in section 5 Conclusion is presented in section6 2 MODIFIED RADIX 4 BOOTH WALLACE TREE MULTIPLIER Basic multiplication operation consists of three Parts partial product generation partial product accumulation and addition and final addition to obtain the product Radix 4 booth multiplier encoding method is discussed in this section A well organized booth encoding method is proposed in this section with careful design considerations The architecture comprises five parts as shown in figure 2 1 Booth encoder Partial product Generator Wallace Tree Formation CSLA Carry Select Adder Sign converter